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Simple integration technique to realize parallel optical interconnects |
Japanese version is also available.
Problem: how to realize integrated and pluggable free-space optoelectronic systems ?
Degrees of freedom in an optical system
Image relay based optoelectronic system. Module 1 and module 2 can be shifted laterally and longitudinally without changing the image position of chip 1 onto chip 2 and vice versa ðThe connection of chip-lens modules is tolerant (to some extent) to lateral and longitudinal misalignments
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Butt-coupling scheme |
ðThe remaining degrees of freedom corresponds to the tilt and the lateral misalignment between chips
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Alignment & integration set-up
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Image analysis process
ðThe chip is aligned with respect to a transparent "target" mask. A machine vision software analyses the misalignment between the targets and the image of the chip devices through the optical system.
Integration process for chips
(a) A reference module composed of a target mask fixed to an optical package that contains half an image relay, is connected to an optical package.
(b) A chip package is mounted on translation and rotation stages and positioned just under the optical package.
(c) The image through the optical system of the chip devices and the targets are observed using a CCD camera. A machine vision software analyzes the misalignment between the target masks. The chip package is then moved using the translation and rotation stages so that the device image are in the center of the targets.
(d) The chip package is fixed to the optical package to form a module. The stages are removed and the modules are disconnected.
1) Componants
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Target mask
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NTT VCSEL array![]()
Hamamatsu photodetector array
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GRIN lens (5mm diameter, 0.2 pitch)
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VCSEL package![]()
Hamamatsu photodetector package
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Optical package
2) Alignement and integration setup
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Alignment set-up for the fabrication of modules3) Modules produced
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Reference module![]()
Test module (target mask instead of chip)![]()
VCSEL module![]()
Photodetector module4) Validation of the integration technique
- VCSEL module connected to the test module
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Target mask from the test module with the image through the GRIN lens relay of the VCSEL arrayThe lateral misalignment between the VCSELs and targets was 20 ± 20µm.- VCSEL module connected to the photodetector module
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Parallel optical interconnects have been successfully obtained at the bitrate of 10Mb/s.
Simple: no processing of the electronic chips and the optics such as a.o. alignment marks, micro pins, holes and grooves is required. No complex packages with multiple elements or sub-mounts are needed. Very few integration steps are necessary to merge the optics with the optoelectronic chips. The connector between modules have few constraining requirements.
Here is a demonstration mpeg file.
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