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SPE-II: A Parallel Optoelectronic Computing System |
Future high-performance computing systems will use electronic and optical technologies to perform the tasks for which they are best suited. Mature electronic technologies can efficiently perform the data processing while optics can be used to provide the high-bandwidth, high connectivity and high density communication paths. The marriage of these technologies is demonstrated in smart-pixel systems. The development of vertical cavity surface-emitting laser (VCSEL) arrays, smart-pixel processing elements, micro-optics, and optoelectronic integrated circuits (OEICs) promise high performance processing systems in the future. Optically interconnected parallel processing systems are ideally suited for the processing of images or 2D patterns. One of the main applications for high-speed optoelectronic machines is real-time image processing for machine vision. Although low-level image processing tasks generally use neighbourhood connections, some high-level tasks such as moment extraction and feature extraction can benefit from global interconnection paths. However, many general purpose high performance processing applications can also utilise the increased computational performance promised by future optoelectronic systems.
The architecture which we propose is based on the pipelined configuration shown in Fig. 1. In contrast to conventional parallel processing systems there are three main differences: the input and output (images or two-dimensional representation of general data) are supplied in parallel; the connections between non-local processors are by optical paths; and the interconnection topology is reconfigurable. The benefits of the first two points are well-recognised. The latter point allows the machine to use an interconnection topology that is best suited to the data-flow structure of the algorithm being performed, and is not fixed as in conventional parallel processors. This ability has the potential to provide improvements in the performance of many algorithms. The processing elements are also general purpose to provide a completely flexible computing machine.
In our present demonstrator we utilise a single smart-pixel PE array to implement a feedback-type system as shown in Fig. 2. The optical outputs are provided by an array of vertical cavity surface emitting lasers (VCSEL). This is imaged through a compact gradient index (GRIN) rod lens system to the photodetector (PD) array. There is a phase modulating SLM on which is displayed computer generated holograms (CGH) to dynamically change the interconnection topology. The outputs from the PD array are directly connected to the processing element array. The PE output drives the VCSEL array, so data is clocked around the circuit in a cyclical fashion. The operation of the PE array can be changed on each cycle, and the interconnection topology can also be periodically changed by updating the pattern on the SLM. The machine is therefore completely programmable and is capable of performing a variety of parallel processing tasks.
Our array of programmable processing elements is based on the Vision Chip project in our laboratory. We have designed each PE to consist of an arithmetic logic unit (ALU) and local memory. The smart-pixel array is a single instruction multiple data-stream (SIMD) type processor which can be programmed by micro-instructions via interfacing to a host computer.
A paper is available online which decribes this project in more detail.
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